1. Field of the Invention
The invention relates to a memory device and in particular to a memory device with dual command access ability.
2. Description of the Related Art
There are two kinds of different memory devices, one is single-port memory device having single access port, and the other is dual-port memory device having two access ports. FIG. 1A shows a schematic circuit of a single-port memory device 100 including a single-port memory array 110 which is accessed according to a pre-charge signal PRE1 and an enable signal EN1. In single-port memory device 100, the pre-charge signal PRE1 and the enable signal EN1 are active while the clock signal CLK triggers. In other words, the control signal PRE1 and EN1 are asserted once in every clock cycle. Therefore, one command, either a read command or a write command, can be accessed in one clock cycle in the single access port.
FIG. 1B shows a schematic circuit of a dual-port memory device 200 including a dual-port memory array 210 which is accessed according to two sets of control signals PRE2, EN2, PRE3 and EN3. The two sets of control signals are active in the similar way of the single-port memory device 100. However, since the dual-port memory device 200 has two access ports, synchronously data read and data write can be achieved. For example, while two sets of pre-charge signals PRE2 and PRE3 and enable signals EN2 and EN3 are asserted, a read command can be accessed in one access port according to the control signal PRE2 and EN2; a write command can be accessed in the other access port according to the control signal PRE3 and EN3. In other words, while one data is written to an address of the dual-port memory array 210, another data can be read from another address therein.
Although synchronously data read and data write is benefited in dual-port memory device 200, the structure is more complicated than the single-port memory device 100 and the number of transistors is also much.